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PhD student in computer architecture at Georgia Tech, working on performance modeling and evaluation of large-scale systems.
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Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together
Published in 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2021
In this work, we designed dead entry predictors for TLBs and caches, particularly focussing on dead-on-arrival (DOA) entries which are common in the L2 TLB. dpPred is a dead page predictor for the TLB and cbPred is a correlating dead block predictor for the cache that uses TLB dead page information to make decisions. On a set of high memory footprint workloads, a combination of dpPred and cbPred achieves 8.3% improvement in IPC.
Filtering Wasteful Vertex Visits in Breadth-First Search
Published in 13th Workshop on Irregular Applications: Architectures and Algorithms - SCW ’23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis
In this work, we analyze distributed Breadth First Search for potential filtering opportunities for the messages transmitted. We identify techniques to reduce the storage requirement for such a filtering logic and discuss implementation considerations for filtering.
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Support for Fast and Reliable VMM Live Upgrades in Libvirt
Published in KVM Forum 2021
This talk discussed an end-to-end solution for live upgrades, i.e. upgrading the hypervisor without a reboot, using local live migration (for KVM/qemu/libvirt). We discussed how to minimize memory and state transfer during a local migration through passing FDs between co-operating qemu processes, orchestrated by libvirt.