Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together
Published in 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2021, 2021
Chandrashis Mazumdar*, Prachatos Mitra*, Arkaprava Basu (* equal contribution)
In this work, we designed dead entry predictors for TLBs and caches, particularly focussing on dead-on-arrival (DOA) entries which are common in the L2 TLB. dpPred is a dead page predictor for the TLB and cbPred is a correlating dead block predictor for the cache that uses TLB dead page information to make decisions. On a set of high memory footprint workloads, a combination of dpPred and cbPred achieves 8.3% improvement in IPC.